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MM74HC374 3-STATE Octal D-Type Flip-Flop
September 1983 Revised February 1999
MM74HC374 3-STATE Octal D-Type Flip-Flop
General Description
The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 20 ns s Wide operating voltage range: 2-6V s Low input current: 1 A maximum s Low quiescent current: 80 A maximum s Compatible with bus-oriented systems s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number MM74HC374WM MM74HC374SJ MM74HC374MTC MM74HC374N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Output Control L L L H L X H L X X H L Q0 Z Clock Data Output
Top View
H = HIGH Level L = LOW Level X = Don't Care = Transition from LOW-to-HIGH Z = High Impedance State Q0 = The level of the output before steady state input conditions were established
(c) 1999 Fairchild Semiconductor Corporation
DS005336.prf
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MM74HC374
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN ) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 35 mA 70 mA -65C to +150C
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 -40 VCC +85 V C 2 Max 6 Units V
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 6.0 mA |IOUT| 7.8 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 6.0 mA |IOUT| 7.8 mA IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 A 6.0V 8.0 80 160 A VIN = VIH, OC = VIH VOUT = VCC or GND 6.0V 0.5 5 10 A VIN = VCC or GND 4.5V 6.0V 6.0V 0.2 0.2 0.26 0.26 0.1 0.33 0.33 1.0 0.4 0.4 1.0 V V A 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 Units V V V V V V
Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC374
AC Electrical Characteristics
VCC = 5V, TA = 25C, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tS tH tW Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q Maximum Output Enable Time Maximum Output Disable Time Minimum Setup Time Minimum Hold Time Minimum Pulse Width 9 RL= k CL=45 pF RL= k CL=5 pF 20 5 16 ns ns ns 19 17 28 25 ns ns CL=45 pF 20 32 ns Conditions Typ 50 Guaranteed Limit 35 Units MHz
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MM74HC374
AC Electrical Characteristics
VCC = 2.0-6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay, Clock to Q CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF tPZH, tPZL Maximum Output Enable Time RL = 1 k CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF tPHZ, tPLZ Maximum Output Disable Time tS Minimum Setup Time RL = 1 k CL = 50 pF 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V tH Minimum Hold Time 2.0V 4.5V 6.0V tW Minimum Pulse Width 2.0V 4.5V 6.0V tTHL, tTLH Maximum Output Rise and Fall Time tr , tf Maximum Input Rise and Fall Time, Clock CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance (per flip-flop) OC = VCC OC=GND 30 50 5 10 10 10 pF pF pF CL = 50 pF 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 30 9 8 25 7 6 50 80 21 30 19 26 50 21 19 150 200 30 40 26 35 150 30 26 50 9 9 5 5 5 80 16 14 60 12 10 1000 500 400 189 250 37 50 31 44 189 37 31 60 13 11 30 5 5 100 20 18 75 15 13 1000 500 400 225 300 45 60 39 53 225 45 39 75 15 13 5 5 5 120 24 20 90 18 15 1000 500 400 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions CL = 50 pF VCC 2.0V 4.5V 6.0V 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 68 110 22 30 20 28 TA = 25C Typ 6 30 35 180 230 36 46 31 40 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 5 24 28 225 288 45 57 39 50 4 20 23 270 345 48 69 46 60 Units MHz MHz MHz ns ns ns ns ns ns
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
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MM74HC374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com
MM74HC374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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MM74HC374 3-STATE Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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